September 2016
18
E
mbedded
C
omputing
When Speed matters: From Board to
Board with PCI Express Gen3 at 8 GT/s
By Hans-Joachim Jahn,
IRISO
IRISO’s long-term available
MXM2 connector has been qualified
for suitability with the third
generation of PCI Express. Simulations
from EyeKnowHow have proofed
that IRISO’s connectors are well
suited for use in applications with
data transfer speeds of up to 8 GT/s.
MXM2 connectors have been designed to
connect graphic cards to motherboards. Now
they are widely used for board to board con-
nections in industrial and automotive applica-
tions where many signals are to be connected
at high data rates. Most popular is the use as
a baseboard connector for SGET’s popular
Qseven module standard. When Qseven was
introduced to the market in 2008, SATA2 and
PCI Express (“PCIe”) Gen1.1 with net data
rates of up to 2.5 gigatransactions per second
(GT/s) for each lane were state of the art and
PCIe Gen 2.0 was just being introduced to the
market after its formal release in 2007. Mean-
while PCIe Gen3 is transferring data at 8 GT/s
per lane. While signal transmission at this
speed has been established in many embed-
ded systems for quite some time, so far none
of the connector manufacturers had com-
mitted nor released the suitability for these
speeds with their MXM2 connectors predom-
inantly used in Qseven- and graphics systems.
Early this year Japanese connector manufac-
turer IRISO has got its long-term available
MXM2 connector qualified for suitability
with the signal transmission speeds which
come along with the third generation of PCI
Express („Gen3“). Simulations performed
by German company EyeKnowHow have
proofed that IRISO’s MXM2 connectors are
well suited for use in applications with data
transfer speeds of up to 8 GT/s. Specifically,
signal transmission in Qseven COM Carrier
board scenarios (Device-Up and Device-
Down) has been simulated with PCI Express
Gen3.
The Standardization Group for Embedded
Technology (SGET e.V.) has laid out two
generic cases in their Qseven Specification for
transmission of data between CPU and con-
nected devices: Device Down, where the target
device of the PCIe communication is located
right on the main computer board (“baseboard”
or “carrier board”), which is connected to the
CPU board (here: Computer-on-Module;
“COM”) via a board-to-board connector and
Device Up, where the target device of the PCIe
communication is located on a plug-in module
(“AddIn card”) located on the main computer
board which is connected to the CPU board.
It’s obvious that the second case is more chal-
lenging due to the extra discontinuities on the
signal path caused by the additional connector.
No need to say that for signal integrity reasons
the number of vias has to be kept at an abso-
lute minimum which is defined in the case of
Qseven to a number of three pairs (per dif-
ferential signal) on the CPU module and two
pairs on the baseboard. Figures 2 and 3 show
the respective simulation setup.
Physical board data for the simulation (Layer
stack-up; geometry/routing lengths) have
been taken from an actual Qseven V2.0 CPU
module and the current reference carrier
board and resulted as follows:
n
CPU module: routing length: 3” (7.62
mm); with the DC block after 0.3” routing
length, impedance 85 Ohms +15% tolerance,
Microstrip and Stripline routing, 3 via pairs.
n
Carrier board: impedance 85 Ohms -15%
tolerance, stripline routing, 2 via pairs.
n
AddIn card (Device Up configuration only):
routing length 3.5” (8.89 mm), impedance 85
ohms, 2 via pairs.
Simulation purpose was to sweep the in trans-
mission line length to find out the maximum
length within a given minimum signal qual-
ity at PCI Gen3 speed of 8GT/s and to keep
as close as possible to the adopted PCI SIG
method. First step was to perform end-to-end
simulations of the two configurations (device
up/down) from transmit (TX) pad to receive
(RX) pad and to determine eye height (EH)
and eye width (EW) after reference equalizer
at eye pad using statistical methods. Worst
case scenarios were applied for mismatches
between CPU module and carrier board.
Other parameter worst case effects have been
adopted by setting margins in eye width and
eye height. The simulation was done on base
of genuine models from the manufacturer
for transmitter, TX/RX package and RX load
models. For the channel based on Microstrip
(MS) and Stripline (SL) Layout technology the
Figure 1, The Eye diagram shows
the final result of the connector
simulation with 11” routing length
on the carrier board in Device
Down configuration, i.e. without
further AddIn card on the carrier
board.
