19
September 2016
E
mbedded
C
omputing
layer-stack corresponding MS/SL multilayer
models were used. Models for the vias have
been created with a momentum field solver.
The Iriso Qseven connector model was gen-
erated by port combining and de-embedding
out of physical measured s-parameter data.
After combining of IL, RL, FEXT and NEXT
data with the ADS touchstone combiner util-
ity the final result was a 12 port connector
model. While top and bottom side perfor-
mance was comparable, due to slightly higher
insertion loss the topside data were selected
for channel simulation. With top-to-bottom
crosstalk being less than -50dB at 4 GHz three
differential pairs have been used on one top.
The s-parameters for Device Up simulation
with the assumed standard PCIe connector
have been provided by the vendor.
The step response transient simulation has
been executed with ADS using the CPU ven-
dor models as drivers with the step response
being captured at the RX pad at the end of the
channel. In the next step the step response
waveforms of the victim and two aggressors
have been saved and fed into the simulator for
statistical eye calculation.
The simulation followed PCI-SIG rules with
adding and optimizing TX-PreEmphasis
and RX Equalization settings. As mentioned
before, only impedance mismatch effects have
been directly included into the simulations.
Effects like Corner Case Silicon and others
have been lumped into additional margin.
For Device Down configurations the defined
margin of 20mV (EH) and 15% (EW) can
be provided for routing lengths of up to 11”
(279.4 mm) on the carrier board plus the 3”
(7.62 mm) on the CPU module. For Device
Up configurations the defined margin of 20
mV (EH) and 15% (EW) can be provided for
routing lengths of up to 6” (152.4 mm) on the
carrier board plus the 3” (7.62 mm) on the
CPU module and the assumed 3.5” (8.89mm)
on the AddIn card.
In both configurations the simulation shows
a non-linear behaviour for eye-hight vs. eye-
width. The difference between the total rout-
ing length shows that the PCIe connector and
the additional vias for the add-in card eat
up about 1.5” (38.1 mm) of routing length.
In practice simulated maximum routing
lengths on the base board should be more
than sufficient. With real routing lengths
being significantly shorter, typical margins
will be significantly better than the defined
threshold values. Well and efficient routed
CPU modules and AddIn cards leave more
routing length for the baseboard. The good
simulation results with the relatively high
share of lumped margin show that the accu-
racy of the simulation is good enough. Gen-
erating more accurate results would require
the simulation to be run with exact parameter
adjustments for each individual system.
The simulation results for the Iriso IMSA-
18010S-230A-GN1 substantiate that this
MXM2 connector does its job as baseboard
connector for Qseven pretty well and that it
has enough reserve for even higher speeds
than current PCIe Gen3 with 8 GT/s. The
guaranteed 10 year long term availability
makes it well suitable for long lasting and
long running automotive and industrial
applications, too.
n
Figure 2. Simulation Setup for Device Down
Configuration
Figure 3. Simulation Setup for Device Up
Configuration
Figure 4. Simulation Results Summary: The required Eye Hight margin of at least 20 mV can be
kept while not exceeding 11” (Device Down) respectively 5”(Device Up) routing length on the
carrier board. Eye Width margin of min. 15% is not critical here.
