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February 2015
M
icrocontrollers
& S
o
C
s
ware-programmable-only ASSP implemen-
tations. Adding Xilinx FPGAs to these ASSPs
has helped a plethora of companies differenti-
ate their products in the marketplace. With the
Zynq-7000 All Programmable SoC, Xilinx is
fielding a platform implementation of the stal-
wart ARM Cortex-A9 that suits the vast major-
ity of embedded applications. As illustrated in
table 2, the Zynq SoC offers many advantages
over ASIC, ASSP and even ASSP+FPGA com-
bos as a silicon platform. In comparison to
other hardware implementations of the ARM
processing system, the Zynq SoC has the best
feature set in terms of NRE, flexibility, differ-
entiation, productivity/time-to-market, lowest
cost of derivatives and best overall risk mitiga-
tion. What’s more, the Zynq SoC has vast cost
advantages over other platform implementa-
tions. Let’s look at the numbers.
The average cost of designing a 28-nm ASIC
is $130 million, and thus the 10x revenue goal
amounts to $1.3 billion for ASIC designs. But
typical design projects based on the Zynq SoC
inherently have a much lower overall design
cost and faster time-to-market than ASIC
implementations. That’s because they supply
a predesigned, tested, characterized, verified
and manufactured SoC that provides software,
hardware, I/O performance and flexibility for
differentiation. What’s more, the Zynq SoC
benefits from the fact that Xilinx hardware and
software design tools are inexpensive and are
highly integrated, whereas ASIC tool flows are
complex, have significant interoperability and
compatibility issues, and entail complex licens-
ing with costs running in the millions. Xilinx
design flow is especially streamlined when
designers use the company recommended
UltraFast methodology. In addition IP qual-
ification costs are low because the Xilinx eco-
system IP is already designed and preverified,
while Xilinx tools generate middleware.
As a result a typical Zynq SoC project runs $23
million. Thus, to achieve the standard 10x rev-
enue goal for design projects requires lifetime
revenue of $230 million - a 10x goal that is
far more achievable and feasible than the $1.3
billion required to achieve 10x for an ASIC
implementation. Using the method described
already while analyzing the IBS data, if we
assume that an initial complex design imple-
mented in a Zynq SoC was able to capture
100 percent of the same targeted $1.3 billion
market, it would require only a $23 million
investment using 57 engineers for two years
to bring the product to completion. If we
assume that the initial Zynq SoC design has
the same 20 percent profit margin as the ini-
tial ASIC design, the initial Zynq SoC design
would have an NPV of $107.27 million, with a
Table 1. Creating derivative designs has an impressive net present value (NPV) but even more
impressive profitability index.
Table 2. The Zynq-7000 All Programmable SoC offers the right mix of attributes for customers
looking to implement a platform strategy.
