February 2015
25
M
emories
New flash management architecture
enables MLC for industrial storage
By Susan Heidrich,
Hyperstone
This article describes hyMap™ flash
management architecture,
a new sub-page-based mapping
and flash translation layer approach
which significantly improves write
amplification, increases endurance
and random write performance.
A low random write WAF results in
high random write IOPS, preventing
stress on the flash and giving
the flash device a longer life.
n
Significantly decreased Write Amplification Factor (WAF)
n
Increased 4K random write IOPS and performance
n
Fastest response time and reduced write latency
n
Intelligent Garbage Collection
n
Adaptive Dynamic, Static and Global Wear Levelling
n
Read Disturb Management
n
Dynamic Data Refresh
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Reliable Write for MLC Flashes
n
MLC aware Power Fail Management (PFM)
n
Available for S8 and U8 Flash Memory controllers
Reliable NAND Storage Controllers
HALL 1 | BOOTH 301
hyMap
™
Flash memory is one of the most import-
ant storage technologies in terms of keeping
and quickly accessing large data. This refers to
the consumer market as well as to industrial
applications. For storing and accessing data
on a flash, a storage device controller is nec-
essary. However, not only the controller hard-
ware, but especially the dedicated firmware
with complex algorithms enable safe flash
handling and reliable data management and
allow for market differentiation.
File systems use certain access patterns for
writing to storage systems. The smallest
access unit usually is a sector of 512 bytes.
4 Kbytes is a rather common unit, but it
can be up to 256 Kbytes. There are several
different protocol types such as ATA, USB,
SD or MMC that pass read and write com-
mands either directly or queued to a storage
device controller. In all flash storage sys-
tems, a flash translations layer (FTL) includ-
ing logical to physical mapping is applied
that translates host-side logical to flash-side
physical accesses. According to individual
application requirements in terms of cost,
performance and other desired features,
different mapping approaches and granular-
ities can be applied. The new hyMap™ tech-
nology is targeted to guarantee maximum
reliability and endurance while improving
random performance significantly.
Finer mapping granularity
The smallest read access unit of a NAND
flash can be a sector (512 bytes). The small-
est write access unit is one page. Page sizes
differ among flashes and can be between 2K
to 8K for SLC and 8K to 16K for MLC today.
Another flash-specific feature is the fact that
a block must be erased before pages can be
rewritten. Also block sizes differ depending
on flash technology and capacity and can
range from 128 KB to 8 MB.
Still mostly used within consumer USB flash
drives or SD cards, is “block-based mapping”.
In this approach logical blocks are mapped to
physical blocks. Pages within those blocks are
directly 1:1 allocated between the host view
and the flash view. This means logical page 1
within any block refers to physical page 1 in
the associated physical block.
Another approach is the “page-based mapping”
in which logical pages are mapped to phys-
ical pages. Block numbers are part of the
page address therefore a logical page can be
mapped to any page within any block.
An even finer mapping approach is “sub-page-
based mapping” where logical units smaller
than a page are mapped to physical units.
However, as the smallest possible unit which
can be written to a flash is still one page, those
units need to be consolidated to one page.
When reading that smaller unit the control-
ler does not need to transfer the whole page
from the flash into the controller SRAM. The
finer the granularity of the mapping, the bet-
ter it can be tuned to different usage models.
hyMap™ is sub-page-based by default and can
be compiled to different granularities.
Very low RAM requirements and inherent
power fail safety
The finer the granularity of the mapping, the
more complex is its algorithm. Apart from
providing more computational power, more
mapping information must be stored when
updating, and retrieved when reading. His-
torically, most SSDs have stored all mapping
information in an external DRAM. While
this is convenient and fast, it is very difficult
to ensure power-fail robustness. The average
size of mapping data for a conventional page-
based mapping FTL is in a range of 0.1% of
the drive capacity e.g. 32 MB for 32 GB. For
a sub-page-based mapping it is even higher.
Every time a drive shuts down, this DRAM
content needs to be stored in non-volatile
memory (NVM). For stable operations, super
caps need to be added to ensure power sup-
ply in case of a power loss. Apart from cost,
this introduces another element that would
need to be considered when assessing drive
