communication protocols and video transport
standards. Proprietary standards can also be
supported. By providing flexibility to adjust
and optimise processing resources, the Zynq
SoC contrasts with a conventional DSP or
GPU-based IC which may not provide suffi-
cient compute performance to execute all the
required algorithms within the number of cy-
cles available. An additional standalone FPGA
may be needed to support such an IC.
To help developers take full advantage of the
flexible, configurable resources of the Zynq
device, the Vivado HLS Design Suite dramati-
cally simplifies tasks such as partitioning of
hardware and software, to allow tasks to be
quickly reassigned if they are seen to be re-
stricting performance. Vivado HLS is particu-
larly well suited to embedded-vision applica-
tions, and is designed to be easy to use by de-
velopers who are accustomed to working with
vision algorithms written in C and C++. If an
algorithm is executing too slowly, or is over-
loading the application processor, Vivado HLS
allows developers to automatically synthesise
the algorithm in Verilog or VHDL to run in
the SoC FPGA logic. This eliminates any need
to manually convert C or C++ code into equiv-
alent HDL code, which can add significant de-
velopment time and design risk to the project.
In addition to avoiding this risk, developers
can also take advantage of Vivado HLS to
adjust processor versus logic trade-offs very
quickly at the systems level, and then run the
revised design immediately in the Zynq SoC
to ensure optimal system performance for the
intended application. The Zynq SoC develop-
ment infrastructure provides further support
for embedded vision applications by also in-
cluding the OpenCV industry-standard open-
source library of algorithms that help accelerate
the design of vision systems. The OpenCV
library is continually expanding, and now con-
tains over 2500 algorithms written in C, C++,
Java and Python, which are contributed by
the open-source developer community. This
range from simple functions such as image
filters to advanced functions for analytics such
as motion detection. Vivado HLS allows devel-
opers targeting the Zynq SoC to synthesise or
compile these algorithms into RTL code
optimised for implementation in the SoC
FPGA logic.
Xilinx has also created the SmartCORE IP in-
tellectual property suite, which provides access
to embedded vision IP meeting the needs of
diverse market segments. Developers can quickly
implement SmartCORE IP cores and algorithms
from the OpenCV library within an embedded
vision project using Xilinx IP Integrator, a
plug-and-play tool that supports both schematic
entry and command-line environments.
February 2014
20
M
ICROCONTROLLERS
Hall-Stand 4-206
Altium: new release of TASKING C compiler for
power architecture
Altium announces a new major release of its TASKING C compiler so-
lution for automotive application development, supporting the Power
Architecture based microcontrollers from the Freescale Qorivva/5xxx
series and STMicroelectronics SPC5 series. In addition to various im-
provements on code optimizations for speed and size, the new compiler
brings device support for the MPC56xx and SPC56x microcontroller
series, while also allowing users to develop applications already for new
devices by selecting the corresponding e200 core level.
Hall-Stand 4A-118
SiLabs: 8-bit wireless microcontrollers for IoT
Silicon Labs has expanded its family of 8-bit Si10xx wireless microcon-
trollers with two new options optimized for both cost-sensitive and
performance-intensive designs. By combining its ultra-low-power MCU
technology with its sub-GHz EZRadio and EZRadioPRO transceivers
in a single-chip solution, Silicon Labs has created new energy-friendly
wireless MCUs that achieve industry-leading RF performance with the
lowest overall power consumption in their class. Supporting worldwide
frequency bands from 142 to 1050 MHz with low-power sleep and
active modes for extended battery life, the Si106x and Si108x wireless
MCUs address the low energy and RF connectivity requirements of
home automation, security and access control, sensor networks, asset
tracking and long-range control applications for the Internet of Things.
Hall-Stand 4A-210
Freescale: Kinetis miniature MCUs for next generation
IoT devices
Freescale Semiconductor is extending its Kinetis portfolio of micro-
controllers to include Kinetis miniature MCUs, which offer massive
design potential in a tiny industry leading package. Intelligent devices,
especially in the Internet of Things era where connectivity and portability
is crucial, continue to grow in complexity while shrinking in physical
size. Starting at 1.9 x 2 mm, Kinetis mini MCUs use wafer-level chip-
scale packaging and maintain the scalability and feature rich IP available
across the entire Kinetis portfolio.
