85 operating temperature and high noise im-
munity. These devices form a series of high-
performance 8051 based microcontrollers for
analog and digital signal processing.
Telit expands into M2M cloud services
Telit Wireless Solutions has acquired ILS Tech-
nology LLC (“ILST”). ILST is a provider of
ready-to-use, off-the-shelf cloud platform serv-
ices connecting enterprise IT systems to M2M-
enabled devices as well as machines for busi-
nesses-critical use. ILST solutions are easy to
deploy and can integrate M2M devices with
minimal application development effort. Crit-
ical to its customers’ businesses, ILST services
leverage comprehensive technology and
processes to provide security and full protection
of company and customer data as well as reg-
WIZnet: W5500 hardware TCP/IP chip for
MAC-PHY price
WIZnet pronounce a new offspring in the
3in1 internet-interface chip family. The new
W5500 named chip added beneath the existing
portfolio as power efficient (only 45°C warm)
and only SPI Version. Hardware TCP/IP inter-
net interface controller (pure gate logic +
memory) fromWIZnet is a proven most stable,
powerful and secure interface-solution with
or without OS for embedded internet applica-
tions for more than 10 years. With the W5500
WIZnet now address the volume business up
to the SoC 4in1 Solutions and attack the
classic MAC-PHY Ethernet-Controller (2in1)
directly for same price. WIZnet is no MCU
vendor and totally independent and offer the
chip also as bare-die for highly integrated So-
lutions. For the standard IC-market WIZnet
chose first the LQFP package (48pin, 9x9mm²,
0.5 mm pitch) for easy to use and simple han-
Xilinx announces „All Programmable
Abstractions“ initiative
Xilinx announced the All Programmable Ab-
stractions initiative to improve productivity
of hardware designers and to empower systems
and software developers to directly leverage
All Programmable FPGA, SoCs, and 3D ICs.
Xilinx and its ecosystem Alliance members in-
cluding MathWorks and National Instruments
now support a combination of software, model,
platform, and IP-based design environments.
These environments enable high-level graphical
and text-based programming languages such
as C, C++, SystemC, and will soon support
OpenCL with advanced automation technology
that translates these languages into optimized
Telit selected as key representative
in global roll-out of Galileo positioning
system
TelitWireless Solutions was selected among var-
ious applicant members of the Italian Technology
Industry as one of the nation’s key representatives
in the global roll-out of Europe’s Galileo ultra-
accurate satellite positioning system. The selection
reflects the high degree of credibility demon-
strated by the Italian Government not only in
the bold strategic plan proposed by Telit to ac-
celerate global adoption of the Galileo technology,
but also in the company itself.
Infineon advances trusted computing
with OPTIGA TPM family
Infineon introduced a new family of Trusted
PlatformModules that broaden the application
base for Trusted Computing and mark the
first availability of discrete security chips sup-
porting the next generation TPM 2.0 specifi-
cation. TPMs are specific microcontrollers that
defend computing systems against unautho-
Cadence: mixed-signal low-power design
flow helps SiLabs cut MCU power con-
sumption in half
Cadence announced that Silicon Labs has sig-
nificantly reduced the power consumption of
its latest energy-friendly ARM-based micro-
controller unit by 50 percent using the complete
Cadence mixed-signal low-power design flow.
According to Silicon Labs, the new EFM32
Wonder Gecko, which incorporates an ARM
Cortex-M4 core, uses 50 percent less power
than competitors’ MCUs and extends battery
life for applications running at higher tem-
Altera: free fully verified EtherCAT
Protocol IP
Altera announced the availability of a fully
verified EtherCAT protocol IP for Altera
FPGAs. This announcement is the latest offer-
ing from the collaboration between Altera,
EtherCAT Technology Group and Softing In-
dustrial Automation, for a licensing structure
that gives developers access to leading Industrial
Ethernet protocols with no upfront license
fees, no per-unit royalty reporting or protracted
negotiations, ultimately simplifying the inte-
gration of FPGA-based Industrial Ethernet
Cadence: enhanced system development
suite
Cadence Design Systems introduces the Palla-
dium XP II Verification Computing Platform
as part of an enhanced System Development
Suite, significantly speeding up hardware and
software verification. The Palladium XP II
platform builds on the Palladium XP emulation
technology by boosting verification perform-
ance by up to 50% and extending its capacity
to 2.3 billion gates. With reduced power and
increased gate density, customers can now run
larger payloads in a smaller footprint, reducing
Cadence accelerates chip design with
Virtuoso layout suite
Offering increased design team productivity
and circuit performance for custom ICs, Ca-
dence introduced a groundbreaking approach
to custom design with its Virtuoso Layout
Suite for Electrically Aware Design. This unique
in-design electrical verification capability en-
ables design teams to monitor electrical issues
while a layout is created, rather than wait until
the layout is completed before verifying that it
n intent.
PragmaDev: survey on modeling
technology usage
The survey confirms last year’s results indi-
cating a substantial decrease in UML usage
forecast. At the same time the effective usage
of UML has been slightly growing from 65%
in 2011, to 70% in 2012, up to 71% this year.
These two information probably indicates
UML has reached its peak of expectations and
is about to start its decline to the trough of
disillusionment. On the side, the trends for
the upcoming usage of the other technologies
SEGGER: J-Link adds full support for
Renesas’ FINE Interface
SEGGER has added support for Renesas’ sin-
glewire debug interface FINE to the whole J-
Link family of debug probes. The debug inter-
face FINE is used by the Renesas devices
RX100, RX200 and RX63x. J-Link is the only
silicon vendor independent debug probe in
the market capable of connecting to a device
HCC Embedded contributes FAT file
system to FreeRTOS project
HCC Embedded will contribute a fully func-
tional, FAT compatible file system to the highly
successful FreeRTOS project. Engineers will have
access to ‘FAT SL’ free of charge when using
FreeRTOS+. Developers will be able to download
the source code based file system for evaluation
and training on any MCU target. A license
which permits free use in commercial projects
ounced shortly.
27
October 2013
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