November 2016
42
I
ndustrIal
C
ontrol
& C
omputIng
a typical software solution calculating the
32-bit CRC value consumes nearly 30% of the
overall performance that is generally required
for the Ethernet communication. Thus the
CheckSum accelerator obtains a correspond-
ingly large saving in CPU performance in
high Ethernet traffic situations.
The organization of the frame data buffer for
transmission or reception is normally byte-
wise. Read-access to certain frame header
information requires the collection of all
necessary bytes in the frame buffer and their
rearrangement into the right sequence. For
the transmit direction the rearrangement
must be done in the opposite direction into a
compressed frame format. This data process-
ing typically requires about 15% of the overall
CPU performance for a pure software-based
TCP/IP stack. The Header EnDec accelerator
has the task of automatically rearranging the
data between the compressed frame format
and the CPU-oriented 32-bit aligned format.
With this accelerator the CPU has a well-
suited, fast and direct read and write access
to all frame header information without any
latencies.
The Buffer Management accelerator auto-
matically controls the buffer allocation
and release functions in hardware for the
Ethernet processing.
The basic structure of the R-IN Engine also
provides the capabilities of a flexible host
interface with required functions for process
synchronization and fast and direct access to
the communication data. For a single-core
implementation this interface can be used for
an external host running the system appli-
cation. In a dual-core implementation it is
a chip-internal interface between the R-IN
Engine (communication part) and the main
CPU of the device (application part). In this
sense the R-IN host interface is of course
not an accelerator, but without the need of a
typical communication interface it allows
direct and zero-latency access into the R-IN
Engine and its resources.
Compared with other architectures, the
advantages of the R-IN Engine with its differ-
ent accelerators are reflected in higher CPU
performance and increased stability while
cutting the overall power consumption. The
special hardware works much more efficiently
and greatly relieves the CPU load. Thus R-IN
architectures optionally run the network com-
munication at significantly reduced power
dissipation, or they deliver a significant mar-
gin to compute additional complex tasks in
the application.
With the R-IN Engine architecture described,
a device is able to process at the same time
both network communications and complex
applications, with extremely low delays and
low jitter and minimum power consumption.
Due to the network functions and underlying
structures the R-IN Engine covers not only
all the protocols of the first group using a
standard IEEE 802.3 hardware, but also one
protocol of the second group using a specific
communication controller. Thus a multi-pro-
tocol industrial automation product can sim-
ply be implemented using the flexible and low
cost R-IN single-device approach.
Designed for industrial networks the R-IN
Engine is already successfully integrated into
the R-IN32M3 and in the RZ/T1 families.
While R-IN32M3 is a single-core solution
with members for EtherCAT and CC-Link
IE protocols, the RZ-T1 family is conceptu-
ally dual-core architecture. It basically has
two separate CPUs for communication (ARM
Cortex-M3 inside the R-IN Engine) and
Application (ARM Cortex-R4). RZ/T1 comes
with several derivatives for different product
types. Other devices based on R-IN Engine
are already under preparation or are being
planned.
A further but not negligible advantage for
R-IN software development is the quite sim-
ple protocol porting based upon the re-use
of R-IN Engine hardware in different fami-
lies. This is especially true for all protocols
of the first group which run basically on the
identical standard Ethernet hardware. When
looking to the R-IN32M3-EC device exam-
ple (EC: including EtherCAT Slave Control-
ler, the basic structure directly correlates with
the ideal solution as shown in figure 3. It also
includes the 100 Mbit/s Ethernet PHYs and
requires only a few external components to
run the application and protocol in a single
device. Thus R-IN32M3-EC is indeed a very
good candidate for use in many small indus-
trial Ethernet products. At the same time it is
also perfectly suited for Industry 4.0.
n
Figure 6. Block diagram RZ/T1 (derivative including R-IN Engine)
Figure 5. Block diagram R-IN32M3-EC
