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constraints. Boost NRE (Non-Recurring
Engineering) cost. High investment in engi-
neering resources as the team needs diverse
expertise in both hardware and software. Fur-
ther, product development time is long lead-
ing to inflated engineering cost. High input
cost. Usually, sales volume of embedded prod-
ucts is low. So, OEMs cannot leverage eco-
nomics of scale in low-volume procurement
of components such as SoC, and thus pay
higher prices. Long time-to-market. As the
development happens from scratch, the devel-
opment time increases, meaning long time-to-
market. High development risk. With scratch
development of hardware and software, there
is a high probability that things may go wrong
at any level. This adds significant risk to the
project compromising time-to-market and
development cost. Questionable scalability.
With Moore’s Law in action, the silicon com-
ponents such as SoCs are getting matured in
terms of performance, power-efficiency, and
cost-effectiveness. However, it is impossible to
scale up an embedded platform to accommo-
date these advances without redesign. Prod-
uct risk. There is a substantial risk associated
with the supply chain of the end-product in
case any silicon component (SoC, RAM, flash
memory) reaches the end of life.
SBCs (single board computers) offer a ready-
to-use embedded platform on a single PCB
for developing any end-product. The OEMs
select SBCs that are best suited for their
requirements and then develop the end-appli-
cation. Although SBCs are application-ready,
they suffer from some loopholes. Not scalable:
the SBC approach leads to high switching
cost to migrate to future technologies. As the
CPU is closely coupled with the I/O section
on a single PCB, it is not possible to upgrade
processing power without going for a new
SBC. No customization: customizing a special
SBC for the OEM requirements is not possi-
ble, because the CPU and surrounding I/Os
Figure 2. An illustration of Viola - a small form-factor (74 mm x 74mm), ultra-low-cost carrier
board
